1. Field of the Invention
The invention relates generally to a decoder circuit in a semiconductor memory device, and more particularly to, a decoder circuit capable of reducing its occupation area.
2. Description of the Prior Art
Generally, a semiconductor memory device includes a row decoder and a column decoder. These decoders decode addresses from an address buffer before they are sent to a memory cell.
FIG. 1 is a circuit diagram of a conventional decoder circuit in a semiconductor memory device. The decoder circuit includes a shift register 10 and a driver 20.
The shift register 10 consists of a latch circuit 12 for maintaining the output signal of the driver 20 for a given period of time and a latch circuit 14 for relaying the signal to a shift register at a next stage and maintaining it. The driver 20 is connected to the two latch circuits 12 and 14.
Therefore, large occupation area is needed and the die size is thus increased since these latch circuits 12 and 14 are repeatedly positioned at respective drivers 20. Thus, productivity is degraded due to increased die size.
In order to solve these problems, an object of the present invention is to improve the productivity of semiconductor memory devices by reducing the area occupied by a decoder.
In order to accomplish the above object, a decoder circuit in a semiconductor memory device according to the first aspect of the present invention comprises a plurality of decoder; and a decoder control means for controlling the plurality of decoders in response to an external clock signal and a reset signal, wherein the plurality of decoder drive a plurality of wordlines in response to the output signals of the decoder control means.
A decoder circuit in a semiconductor memory device according to a second aspect of the present invention comprises a decoder control means, a plurality of shift registers and a plurality of drivers. The decoder control means generates an internal reset signal, a plurality of driver enable signals and a plurality of shift register enable signals in response to an external clock signal and a reset signal. The plurality of shift registers generates a plurality of latch signals in response to the internal reset signal and the plurality of shift register enable signals. The plurality of drivers drives a plurality of wordlines in response to the plurality of latch signals and the plurality of driver enable signals, wherein the plurality of shift registers has a loop structure in which an output signal of the shift register at the last stage of the plurality of shift registers is inputted to an input terminal of the shift register at the first stage of the plurality of shift registers.